View AK8817VG_1099635.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ASAHI KASEI
[AK8817]
AK8817
NTSC/PAL Digital Video Encoder
General Description
The AK8817 is a Digital Video Encoder for Portable and Mobile application. ITU-R BT.601 level compatible Y, Cb,and Cr signals which correspond to 27MHz or square pixel are encoded into either NTSC or PAL compatible composite video signal. Interface is made in HSYNC-, VSYNC- synchronized slave-mode operation or ITU-R.Bt656. AK8817 has 75ohm driver with LPF. It is possible to encode the VBID(CGMS-A) and WSS signal on the output video signal. Host Control interface is I2C Bus I/F.
Features * * * * * * * * * * * * * * * * * *
NTSC-M, PAL-B, D, G, H, I Composite Video encoding Y:Cb:Cr 4:2:2 H/V Slave Operation / ITU-R.BT656 Interface Y filtering: 2 x over-sampling C filtering: 4 x over-sampling 9bit DAC Setup VBID ( CGMS-A ) Compatible WSS Compatible Operation Clock rate : 27MHz or Square-pixel Clock rate(NTSC:24.5454MHz/PAL29.50MHz) Video Amp with LPF On-chip Color Bar Output Black Burst Output Power Supply (AVDD, DVDD) 2.7V - 3.3V I/F Power Supply (PVDD) 1.6V - 3.3V Power Down mode Monolithic CMOS 41pin FBGA(4mm x 4mm) (Pb Free)
MS0413-E-03
1
2006 / 05
ASAHI KASEI
[AK8817]
Block Diagram
CLKIN CLKINV RSTN PDN SCL SDA VREF
CLK Generator u-p I/F Register Timing Controller VDI HDI D[7:0] Synchronization Control Input Data Control
CGMS
VREF Generator
IREF
SYNC Generator Y Cb Cr U Cos SubCarrier Generator Sin V C Chroma LPF Filter (x 2 Interpolator) TEST LOGIC 6dB AMP LPF
SAG VOUT
Y LPF Filter (x 2 Interpolator) 9-bit DAC
Cb/Cr LPF Filter (x 2 Interpolator)
DACOUT
Color Bar Gen B.B. Gen
UD[4:0]
PVDD PVSS DVDD DVSS
AVDD AVSS
TEST ATPG
MS0413-E-03
2
2006 / 05
ASAHI KASEI
[AK8817]
Ordering Guide
AK8817VG 41pin FBGA
Pin Assignment
7 6 5 4 3 2 1 A B C D E F G
Bottom View 1 NC AVDD VREF UD3 UD1 CLKINV NC 2 DACOUT AVSS IREF UD4 UD2 UD0 CLKIN 3 SAG BVSS INDEX DVSS DVDD 4 VOUT DVSS 5 DVDD PDN 6 RSTN SCL HDI PVSS D0 D3 D2 7 NC ATPG SDA VDI PVDD D1 TEST
A B C D E F G
D7 D6
D5 D4
TOP View
MS0413-E-03
3
2006 / 05
ASAHI KASEI
[AK8817]
Pin Functional Description
Pin# Pin Name I/O Functional Outline Clock input pin. Input a clock which is synchronized with data. When to input 601 data : 27 MHz. When to input square pixel data : 24.5454 MHz ( NTSC )/ 29.50 MHz ( PAL ) Internal clock is inverted (internal operation timing edge is inverted.) Connect to either PVDD or PVSS(DGND). Power Down Pin. After returning from PD mode to normal operation, RESET Sequence should be done to AK8817. "L "(GND level): Power-down "H ": normal operation Reset input pin. In order to initialize the device , an initialization must be made in accordance with the reset sequence. "L " : reset "H " : normal operation Hi-Z input is acceptable to this pin at PDN = L. I2C data pin. This pin is pulled-up to PVDD. Hi-Z input is possible when PDN is at low. SDA input is not accepted during the reset sequence operation. I2C clock input pin An input level of lower-than-PVDD should be input. Hi-Z input is possible when PDN is at low. SCL input is not accepted during the reset sequence operation. Data Video Signal input pin (MSB). Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Data Video Signal input pin (LSB). Hi-Z input is acceptable to this pin at PDN = L. Horizontal SYNC signal input pin. Hi-Z input is acceptable to this pin at PDN = L. Vertical SYNC signal input pin. Hi-Z input is acceptable to this pin at PDN = L. On-chip VREF output pin. AVSS level is output on this pin at PDN = L. Connect this pin to Analog Ground via a 0.1 uF or larger capacitor. IREF output pin. Connect this pin to Analog ground via a 12k ohm resistor ( better than +/- 1% accuracy ). DAC output pin. Connect this pin to Analog ground via a 390 ohm resistor ( better than +/- 1% accuracy ). Video output pin. SAG Compensation Input pin Analog power supply pin. Analog ground pin. Digital power supply pin (digital core power supply). Digital ground pin (digital core ground). Power supply pin for chip pad. Ground pin for PVDD. Substrate ground pin. Connect this pin to Analog ground
G2 F1 B5
CLKIN CLKINV PDN
I I I
A6
RSTN
I
C7
SDA
I
B6 F4 G4 F5 G5 F6 G6 F7 E6 C6 D7 C1 C2 A2 A4 A3 B1 B2 A5, G3 B4, F3 E7 D6 B3
SCL D7 D6 D5 D4 D3 D2 D1 D0 HDI VDI VREF IREF DACOUT VOUT SAG AVDD AVSS DVDD DVSS PVDD PVSS BVSS
I I I I I I I I I I I O O O O I/O P G P G P G G
MS0413-E-03
4
2006 / 05
ASAHI KASEI G7 B7 D2 D1 E2 E1 F2 C3 A1, A7, G1 TEST ATPG UD4 UD3 UD2 UD1 UD0 N.C. N.C. I I O O O I/O I/O For normal operation, connect to ground. For normal operation, connect to ground. Test output pin. For normal operation, left open. Test output pin. For normal operation, left open. Test output pin. For normal operation, left open. Test I/O pin. For normal operation, left open. Test I/O pin. For normal operation, left open. Index pin. For normal operation, left open. For normal operation, left open.
[AK8817]
Analog Output pin status MODE / PIN name PDNL PDN=HDAC=L VIDEOAMP=L PDN=HDAC=H VIDEOAMP=L PDN=HDAC=H VIDEOAMP=H IREF Hi-Z Output Output Output VREF Hi-Z Outpu Output Output DACOUT Hi-Z Hi-Z DAC Power Down Output Output VOUT Hi-Z Hi-Z VIDEOAMP Power Down VIDEOAMP Power Down(1) Output
DAC: Sub Address 0x00 bit7 0: L->DACOFF 1: H->DACON VIDEOAMP: Sub Address 0x01 bit3,4 00: L->VIDEOAMP_OFF 01,10: H-> VIDEOAMP_ON Note1) Video Amp becomes power down. Since DACOUT pin and VOUT pin are connected with RESISTOR in the LSI, DACOUT pin are not Hi-Z. In case of using only DAC, VOUT pin and SAG pin should be open states.
MS0413-E-03
5
2006 / 05
ASAHI KASEI
[AK8817]
Electrical Characteristics
(1) Absolute Maximum Ratings Parameter Supply voltage DVDD, AVDD, PVDD Digital Input pin voltage (VinP) Input pin current (Iin) Min -0.3 Max 4.5 Units V D[7:0], HDI, VDI, RSTN, PDN, CLKIN, CLKINV,SCL, SDA Exclude Power supply pin. Note
-0.3
PVDD +0.3
V
-10
10
mA
-40 Storage temperature 125 C (Note1) Power supply voltages are values where each ground pin ( DVSS = AVSS = PVSS ) is at 0 V( voltage reference ). All power supply ground pins DVSS, AVSS and PVSS should be at same potential. (2) Recommended Operating Conditions Parameter Min Typ. Max Units Conditions Supply voltage * 3.0 3.3 V AVDD = DVDD 2.7 AVDD,DVDD Interface power supply 1.6 1.8 DVDD V PVDD Operating temperature -30 85 C (Ta) * Power supply voltages are values where each ground pin ( PVSS = AVSS = PVSS ) is at 0 V( voltage reference ). All power supply ground pins DVSS, AVSS and PVSS should be at same potential. (3) DC Characteristics < Operating voltage: DVDD 2.7V~3.3V / PVDD 1.6 V~DVDD, loading condition 15 pF, temperature -30~+85C > Parameter Symbol Min Typ Max Units Conditions Digital input H voltage (VIH) Digital input L voltage (VIL) Digital input leak current I2C (SDA) L output VIH VIL IL VOLC 0.8PVDD 0.2PVDD +/-10 0.4 V V uA V IOLC = 3mA PVDD=1.6 - DVDD PVDD=1.6 - DVDD
( Note ) Digital output pins refer to D[7:0], HDI, VDI, PDN, RSTN, SCL, SDA,CLKIN and CLKINV pin outputs in general term.
MS0413-E-03
6
2006 / 05
ASAHI KASEI (4) Analog Characteristics
[AK8817]
< AVDD = 3.0 V, temperature 25 C > Max Units bit +/- 2.0 LSB +/- 1.0 LSB 1.18 1.38 V Note1) 5.0 mV Note2) 5.0 6.0 7.0 dB Amp Input Level 1Vpp 2.0 Vpp Note3) 100kHz - 5.5MHz Note4) -45 -51 dB 100kHz - 5.5MHz Note4) 54 dB 100kHz - 5.5MHz LPF Ripple -1 +/- 0.5 +1 dB 0dB = 100kHz input 27MHz LPF Stop Band Level 20 30 dB 0dB = 100kHz input LPF Group Delay 10 100 ns |GD3MHz - GD6MHz| On-chip reference voltage (VREF) 1.17 1.23 1.30 V Reference voltage drift -50 ppm/C Note1) Values are when a 390 ohm output load, a 12k ohm IREF pin resistor and on-chip VREF are used. Full scale output current is calculated as Iout = full scale output voltage ( typ. 1.28 V ) / 390 ohm = typ. 3.28 mA. Note2) A voltage referenced to VSS when a decimal zero voltage is input to DAC. Note3) VOUT Output Level Output Load Resistor: 150ohm, Load Capacitor: 15pF Internal Color Bar output Note4) Output signal from DAC to which Input data corresponded 1Vpp. This signal is input to AMP. Load resistor is 150ohm and Load capacitor is 15pF as shown bellow figure at (5) Current Consumption. Parameter DAC resolution DAC integral non-linearity ( error ) DAC differential non-linearity ( error ) DAC output full scale voltage DAC output offset voltage Video Amp Output Gain Video Amp Full scale Level Video Amp THD Video Amp S/N Symbol Min 9 +/- 0.6 +/- 0.4 1.28 Typ (5) Current consumption < Operating voltage : DVDD = AVDD = PVDD = 3.0 V, Ta = +25 C > Parameter Symbol Min Typ Max Units Total power consumption 27 35 mA Note1) Power-down current 1 10 30 uA Note2) Digital part operating current 1 13 mA Note3) Analog part operating current 1 14 mA Note4) Analog part operating current 2 5.5 mA Note5) Analog part operating current 3 0.8 mA Note6) Note1) operation at 27 MHz, NTSC mode on-chip 75% color bar output is enabled and Video Amp output is " on " ( no external output loads are connected except for recommended components. ). 15pF capacitors in following figure represent PCB layout-capacitor. AK8817 SAG 47uF VOUT 15pF 15pF 75ohm VOUT 15pF 15pF 75ohm 1uF 75ohm AK8817 SAG 100uF 75ohm
SAG Compensation ON
SAG Compensation OFF
Note2) measuring conditions : input / output settings after power-down sequence are, PDN pin is at GND level, CLKOUT and SDO output are at high level ( power supply voltage ) with no external connection, input voltage on those input pins is 1/2 level of power supply which are set to accept Hi-Z input at power-down, and TEST = ATPG = GND ( or left open ). Power supplies are AVDD = DVSS = PVDD. Each ground pin ( DVSS, AVSS, PVSS ) is always 0 V ( voltage reference ). Note3) Operation at 27 MHz, NTSC mode on-chip 75% color bar output is enabled. Note4) DAC ON, Video Amp On SAG Compensation On Note5) DAC ON, Video Amp Off (SAG Compensation Off) Note6) DAC Off, Video Amp Off (SAG Compensation Off)
MS0413-E-03
7
2006 / 05
ASAHI KASEI
[AK8817]
AC Timing
< DVDD 2.7 V ~ 3.3 V / PVDD 1.6 V ~ DVDD, Ta at -30 ~ +85 C > loading condition : CL = 15 pF (1) CLK
fCLKI tCLKIL tCLKIH
1/2 PVDD VIH
CLKIN
VIL
Parameter
Symbol
Min.
Typ. 24.5454
Max
Unit
Conditions PIXRT=1 NTSC PIXRT=0 NTSC/PA PIXRT=1 PAL
CLKIN
fCLKI
27 29.50
MHz
CLK duty ratio CLK Accuracy
pCLKID
40
60 100
% ppm
tCLKIL, tCLKIH : minimum pulse width 12 nS ( tr/tf10%-90%Level Rising/Falling time 2nS)
MS0413-E-03
8
2006 / 05
ASAHI KASEI (2) Pixel Data Input Timing
[AK8817]
VIH CLKIN tDS D[7:0] HDI VDI tDH VIL
CLKINV = Low Parameter Data Setup Time Data Hold Time Symbol tDS tDH Min. 5 8 Typ. Max Unit nsec nsec Conditions
When CLKINV = High, similar tDS and tDH are specified at the falling edge of CLKOUT. (3) HSYNC pulse width
pHSW HSYNC
Parameter
Symbol
Min. 15
Typ. 116 128 139
Max
Unit
Conditions NTSC (24.5454MHz)
HDI Pulse Width
pHSW
15 15
CLKs
27MHz
PAL (29.50MHz) * typical values are calculated by converting the HSYNC pulse width of Analog Video specification into number of system clock pulses.
MS0413-E-03
9
2006 / 05
ASAHI KASEI (4) Reset (4-1) Reset Timing
[AK8817]
RSTN pRES 1 CLKIN 2 99 100
Parameter RSTN Pulse Width
Symbol pRES
Min. 100
Typ.
Max
Unit CLKs
(4-2) Power Down Sequence / Reset Sequence Before PDN setting ( PDN to low ), Reset must be enabled for a duration of longer-than-100 clock time. After PDN release ( PDN to high ), Reset must be enabled for 10 mS or longer till analog part reference voltage & current are stabilized.
CLKIN
(CLKOUT=H)
sRES
RSTN
hRES
VIH VIL
PDN GND
VIH
Parameter RSTN Pulse Width
Symbol sRES
Min. 100
Typ.
Max
Unit CLKs
Time from PDN to high to RSTN to hRES 10 msec high SCL low duration before RSTN to tSCLL 50 nsec rise At power-down, all control signals must be surely connected to either the selected power supply or ground level, and not to VIH / VIL levels.
MS0413-E-03
10
2006 / 05
ASAHI KASEI
[AK8817]
(4-3) Power Down Sequence/Power up sequence
AVDD/DVDD PVDD PDN RSTN
VREF
10mS(min) Recover from Power Down state
(4-4) Power On Reset
After Power up, It is necessary to make reset sequence until Analog Reference voltage(VREF) becomes stable. PVDD/DVDD/AVDD should be power up at same time or 1st PVDD power up and AVDD/DVDD makes up.
2.7V
AVDD DVDD
1.6V PVDD
0.8PVDD PDN
RSTN 0.2PVDD
VREF
10mS(min)
item RESETN Pulse width
Symbol pRES_PON
Min 10
Typ
Max
Unit msec
Note
Remark: Reset sequence requires clock input.
MS0413-E-03
11
2006 / 05
ASAHI KASEI (5) I2C Bus Input/Output Timing < Ta = -30 ~ +85 C >
[AK8817]
tBUF SDA
tHD:STA
tR
tF
tSU:STO VSDAH VSDAL
tF SCL tLOW
tR
VSDAH VSDAL tSU:STA
(5-1) Timing 1 VSDAH: 0.8PVDD VSDAL : 0.2PVDD Parameter Bus Free Time Hold Time (Start Condition) Clock Pulse Low Time Input Signal Rise Time Input Signal Fall Time Setup Time(Start Condition) Setup Time(Stop Condition) Symbol tBUF tHD:STA tLOW tR tF tSU:STA tSU:STO 0.6 0.6 Min. 1.3 0.6 1.3 300 300 Max. Unit usec usec usec nsec nsec usec usec
The above I2C bus related timing is specified by the I2C Bus Specification, and it is not limited by the device performance. For details, please refer to the I2C Bus Specification. (5-2) Timing 2
tHD:DAT
SDA tHIGH
VSDAH VSDAL
SCL tSU:DAT
VSDAH VSDAL
VSDAH: 0.8PVDD VSDAL : 0.2PVDD Parameter Data Setup Time Data Hold Time Clock Pulse High Time Symbol tSU:DAT tHD:DAT tHIGH Min. 100 (note1) 0.0 0.6 0.9 (note2) Max. Unit nsec usec usec
note 1 : when to use I2C Bus Standard mode, tSU:DAT >- 250 ns must be met. note 2 : when the AK8817 is used in such bus interface where tLOW is not extended ( at minimum specification of tLOW ), this condition must be met.
MS0413-E-03
12
2006 / 05
ASAHI KASEI
[AK8817]
Device Control Interface
The AK8817 is controlled via I2C Bus Control Interface. [ I2C SLAVE Address ] 2C Slave Address is 0x40 [ I2C Control Sequence ] (1) Write Sequence When the Slave Address of the AK8817 Write mode is received at the first byte, Sub Address at the second byte and Data at the third and succeeding bytes are received. There are 2 operations in Write Sequence - a sequence to write at every single byte, and a sequential write operation to write multiple bytes successively. (a) 1 Byte Write Sequence Slave S w A Address 8-bits 1bit
Sub Address 8-bits
A 1bit
Data 8-bits
A 1bit
Stp
(b) Multiple Bytes ( m-bytes ) Write Sequence ( Sequential Write Operation ) Sub Slave Data(n+ S w A Address A Data(n) A Address 1) (n) 8-bits 1bit 8-bits 1bit 8-bits 1bit 8-bits
A 1bit
....
Data(n+m) 8-bits
A 1bit
stp
(2) Read Sequence When the Slave Address of the AK8817 Read mode is received, Data at the second and succeeding bytes are transmitted.
S Slave Address w A Sub Address (n) A rS Slave Address R A Data1 A Data2 A Data3 A ... Data n stp
8-bits
1
8-bits
1
8-bits
1
8-bits
1
8-bits
1
8-bits
1
8-bits
1
Abbreviated terms listed above mean : S, rS A Astp R/W : Start Condition : Acknowledge ( SDA Low ) : Not Acknowledge ( SDA High ) : Stop Condition 1 : Read 0 : Write : to be controlled by the Master Device. Micro-computer interface is output normally . : to be controlled by the Slave Device. To be output by the AK8817.
MS0413-E-03
13
2006 / 05
ASAHI KASEI
[AK8817]
Video Encoder Functional Outline
(1) Reset (1-1) Reset of Serial Interface part ( asynchronous reset ) Reset is made by setting RSTN pin to low. (1-2) Reset of other than Serial Interface blocks Reset is made by keeping RSTN pin low for a longer than 100 clock time, in normal operation. (1-3) at Power-On-Reset ( including power-down release case ) Follow the power-on-reset sequence. At the completion of each initialization, all internal registers are set to default values ( refer to Register Map ). Right after the reset, Video output of the AK8817 is put into Hi-Z condition. (2) Power-Down It is possible to put the device into power-down mode by setting the AK8817 power-down pin to GND. Transition to power-down mode should be followed by the power-down sequence. As for the recover from the power-down mode, it should be followed by the power-down release sequence. (3) Master Clock A following clock should be input as a Master clock. In Encoder Mode operation ( a synchronized clock with input data is required ) When ITU-R BT.601 data is input When Square Pixel data is input ( PIXRT-bit = 0 ) ( PIXRT-bit = 1 ) NTSC Encoder 27MHz 24.5454MHz PAL Encoder 27MHz 29.50MHz (4) Video Signal Interface Video input signal ( data ) should be synchronized in either of the following methods : * Slave mode operation where synchronization is made with HSYNC ( HDI ) / VSYNC ( VDI ). * ITU-R BT. 656 I / F ( EAV decode ) (only 27MHz operation) (5) Pixel Data Input data to the AK8817 is YCbCr ( 4:2:2 ). Data with Y : 16 ~ 235 and CbCr : 16 ~ 240
should be input.
(6) Video Signal Conversion Video Re-Composition module converts the multiplexed data ( ITU-R BT.601 Level Y, Cb, Cr ) into interlaced NTSC-M and PAL-B, D, G, H, I data. Video encoding setting is done by "Control 1 Register ".
MS0413-E-03
14
2006 / 05
ASAHI KASEI (7) Luminance Signal Filter ( Luma Filter ) Luminance signal is output via LPF ( see x2 Luma Filter in the block diagram ).
10 0 -10 Gain[dB] -20 -30 -40 -50 frequency[MHz]
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
[AK8817]
(8) Chroma Signal Filter ( Chroma Filter ) Chroma input signal components ( Cb, Cr ) prior to the modulation go through a 1.3 MHz Band Limiting Filter ( see 4:2:2 to 4:4:4 x2 interpolator in the block diagram ). Chroma signal which is modulated by the sub-carrier is output via a low pass filter ( Chroma LPF in the block diagram ). Frequency response of each filter is shown below. 4:2:2 to 4:4:4 Interpolator Filter
10 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
-10 Gain[dB] -20 -30 -40 -50 Frequency[MHz]
x 2 Interpolator Filter
10 0 -10 Gain[dB] -20 -30 -40 -50 frequency[MHz]
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
MS0413-E-03
15
2006 / 05
ASAHI KASEI (9) Color Burst Signal Burst signal is generated by a 32 bit digital frequency synthesizer. Color Burst Frequency is selected by mode setting of NTSC / PAL. Standerd NTSC-M PAL-B,D,G,H,I Subcarrier Freq (MHz) 3.57954545 4.43361875 Burst Signal Table (10) Sub - Carrier Reset A function to reset sub-carrier by Color Frame sequence. Reset function can be turned "OFF " by setting SCR-bit of Control 1 Register. Default value is set to enable Sub-carrier reset. SCR NTSC PAL 0 Sub-carrier phase is reset in every 2 Frames ( 4 Fields ) Sub-carrier phase is reset inevery 4 Frames ( 8 Fields ) 1 Sub-carrier reset is not done Sub-carrier reset is not done Video Process 1 VMOD-bit 0 1
[AK8817]
(11) Setup processing Setup processing can be performed on Video signal by Control 2 Register Setup-bit. Following processing is made on Luminance signal ( Y signal ) and Chroma signal ( C signal ) by the Setup processing. Y Setup = Y x 0.925 + 7.5 IRE where Y setup is the Luminance signal after Setup processing. C Setup = C x 0.925 where C Setup is the Chroma signal after Setup processing. (12) Video DAC The AK8817 has a 9 Bit resolution, current-drive DAC as a video DAC which runs at 29.5 / 24.5454 MHz or 27.00MHz clock frequency. This DAC is designed to output 1.28 V o-p at full scale under the following conditions loading resistance of 390 ohms, VREF at 1.23 V and IREF pin resistor of 12k ohms. [ VREF ] pin should be connected to ground via a 0.1 uF or larger capacitor. DAC output can be turned "ON" or "OFF" by register setting and current consumption can be lowered. When the output is turned off, it is put into high impedance condition.
MS0413-E-03
16
2006 / 05
ASAHI KASEI
[AK8817]
(13) Video Amp AK8817 has Video amp that can drive 150ohm with Low pass filter. It can also possible to compensate SAG distortion. To compensate SAG external capacitor is 47uF and 1uF as shown following figure. Recommendation voltage when SAG compensation circuit is used is 3V or more. VOUT pin and SAG pin should be shorten when SAG Compensation is not used. Output pin should make AC coupling. SAG Compensation circuit can be set on or off with setting register. In case of not using internal Video amp (Only DAC use case), Video Amp becomes power down. In this case SAG and VOUT should be Open.
AK8817 SAG VOUT
1uF
75ohm
AK8817 SAG VOUT
100uF 75ohm
47uF
SAG Compensation ON VAMPMD[1:0] 00 01 10 11 Operation Video Amp OFF + SAG Compensation OFF Video AMP ON + SAG Compensation ON Video Amp ON + No SAG Compensation Reserved
SAG Compensation Off Conditions Only DAC output Recommendation Voltage of DVDD/AVDD is 3v or more. SAG pin and VOUT should be shorten.
MS0413-E-03
17
2006 / 05
ASAHI KASEI (14) Video Data Interface Timing Data is captured by a clock which is fed on CLKIN pin. The Video Encoder receives a clock from a controller ( refer to the following diagram ). In Slave mode operation, Synchronization is made with HDI / VDI. In ITU-R BT.656 mode operation, HDI / VDI are not required.
[AK8817]
C L K IN (H D I) C o n t r o lle r (V D I) D [7 :0 ] AK8817
MS0413-E-03
18
2006 / 05
ASAHI KASEI (14-2) Video Interface mode The AK8817 synchronizes with input signal by the following, 2 interface modes. (a) Slave-mode interface where synchronization is made with externally-fed synchronization signals HDI / VDI ( HDI / VDI interface ) (b) ITU-R BT.656 Interface mode ( 656 interface ) interface mode setting is controlled by [REC656]-bit of Control 2 Register. REC656-bit 0 1 Operation HDI / VDI Slave mode ITU-R BT.656 Interface mode
[AK8817]
(a-1) Timing signal ( HDI / VDI ) VS Data input relation Horizontal Synchronization ( in-line Pixel Sync ) is made with HDI synchronization timing signal. Vertical Synchronization ( in-line Frame Line Sync ) is made with VDI synchronization timing signal. Recognition of Video Field ( Odd Field or Even Field ) is made by VDI input signal which is referenced with HDI. In normal operation, the AK8817 checks changes of HDI and VDI at the clock edge ( CLK synchronization ) which becomes a data capture reference position. At a pixel position where HDI is judged to become " Low ", it is recognized as 0H (zero th position ). Cb0 data position depends on input data rate ( ITU-R BT.601 or Square Pixel data ). Cb0 Data NTSC Encoder PAL Encoder At ITU-R BT.601 Data input 244th data 264th data At Square Pixel data input 236th data 310th data
Video Field is recognized by the VDI relation with HDI. Field recognition is made as follows : The AK8817 distinguishes at every Field if it is Odd Field ( 1st Field ) or not. Even Field Sync signal is not usually input. 1 ) Recognition timing of Odd Field is decided by those timing signal relations which are fed on HDI and VDI pins. When the VDI falling pulse is input on VDI input pin during the time from 3 clocks prior to the falling edge of HDI timing pulse which is fed on HDI input till 3 clocks prior to the rising edge of HDI timing pulse, the Line is recognized to be Line 4.
Line4/Line1(NTSC/PAL) HDI Line5/Line2(NTSC/PAL) Line6/Line3(NTSC/PAL)
3CLK VDI
3CLK
2 ) Whenever Horizontal / Vertical SYNC signal inputs are not fed as expected in the Video Specifications, in term of timing and # of pulses ( kept at " High " level ), the AK8817 continues to self-run the operation which is based on the Sync signals, fed just before. But it is recommended to feed Sync signals as specified every time in order to prevent erroneous operation. 3 ) VD pulse input at other than Odd Field synchronization is ignored ( Synchronization is made with Odd Field only ).
MS0413-E-03
19
2006 / 05
ASAHI KASEI (a-2) Horizontal Synchronization ( Pixel Data synchronization within a Line ) (a-2-1) at ITU-R BT. 601 data input case (a-2-1-1) NTSC
1715 CLKIN (27.00MHz) DTI[7:0] HDI 244T Active Video Area 720 x 2 Clock (0x10) (0x80) (0x10) (0x80) (0x10) Cb0 0H 0 244 245 246 247 248 1683 1684
[AK8817]
1713 1714
Y0
Cr0
Y1
Cb1
Cr359 Y719 (0x80) (0x10) (0x10) (0x80)
* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817 takes input data at the falling edge of each CLKIN if CLKEDGE-bit = 1.(CLKINV = 1.) * ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF codes in non Hi-Z state should be input. (a-2-1-2) PAL
1727 CLKIN (27.00MHz) DTI[7:0] HDI 264T Active Video Area 720 x 2 Clock (0x10) (0x80) (0x10) (0x80) (0x10) Cb0 H0 0 264 265 266 267 268 1702 1703 1704 1725 1726
Y0
Cr0
Y1
Cb1
Cr359 Y719 (0x80) (0x10) (0x10) (0x80)
*) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817 takes input data at the falling edge of each CLKIN if CLKEDGE-bit = 1. .( CLKINV = 1.) * ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF codes in non Hi-Z state should be input.
MS0413-E-03
20
2006 / 05
ASAHI KASEI (a-2-2) at Square Pixel Rate input case (a-2-2-1) NTSC
1559 CLKIN (24.5454MHz) D[7:0] HDI Active Video Area 640 x 2 Clock (0x10) (0x80) (0x10) (0x80) (0x10) Cb0 H0 0 TBD 236 237 238 239 240 1514 1515
[AK8817]
1516
Y0
Cr0
Y1
Cb1
Cr319 Y639 (0x80) (0x10)
* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817 takes input data at the falling edge of each CLKIN if CLKINV = 1. * ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF codes in non Hi-Z state should be input. (a-2-2-2) PAL
1887 0
TBD
310
311
312
313
314
1844
1845
1846
CLKIN (29.5MHz) D[7:0] HDI
Active Video Area 768 x 2 Clock (0x10) (0x80) (0x10) (0x80) (0x10)
Cb0
Y0
Cr0
Y1
Cb1
Cr383 Y767 (0x80) (0x10)
H0
* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817 takes input data at the falling edge of each CLKIN if CLKINV-bit = 1. .(CLKINV = 1.) * ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF codes in non Hi-Z state should be input.
MS0413-E-03
21
2006 / 05
ASAHI KASEI ( a-3 ) HDI and VDI relation in each Frame ( a-3-1 ) NTSC ( Frame ) 525 Line The First Field ( ODD ) 263 lines 240 lines 525 HDI VDI 1 2 3 4 5 6 7 22 23 261 262 263 264 480 active lines
[AK8817]
* )VDI negative-going should be fed during the time from 3 clocks prior to negative-going of HDI at L4 till 3 clocks prior to positive-going of HDI. VDI positive-going can occurs at arbitrary location, but keep VDI low for 3 line duration time as a rough idea. The Second Field ( EVEN ) 262 lines 240 lines 263 HDI VDI High 264 265 266 267 268 269 270 285 286 524 525 1 2
* ) VDI negative-going is not required for the Second Field. It is required for the First Field only ( VDI fed during the Second Field is ignored ).
MS0413-E-03
22
2006 / 05
ASAHI KASEI ( a-3-2 ) PAL ( Frame ) 625 Line The First Field ( ODD ) 313lines 288lines 625 HDI VDI * ) VDI negative-going should be fed during the time from 3 clocks prior to negative-going of HDI at L1 till 3 clocks prior to positive-going of HDI. VDI positive-going can occur at arbitrary location, but as a rough idea, keep VDI low for 2.5, or 2 or 3 line- duration time. Data fed at Line 23 is not output on Video output The Second Field (EVEN) 313lines 288lines 313 HDI VDI High 314 315 316 317 318 335 336 337 623 624 625 1 1 2 3 4 5 22 23 24 310 311 312 313 576 active lines
[AK8817]
314
2
*) VDI negative-going is not required for the Second Field. It is required for the First Field only ( VDI fed during the Second Field is ignored ). Data fed at Line 623 is not output.
MS0413-E-03
23
2006 / 05
ASAHI KASEI
[AK8817]
( b-1 ) ITU-R BT.656 Interface mode The AK8817 makes a synchronization with an incoming signal by decoding EAV in the signal when ITU-R BT.656 encoded signal is input. EAV code is located at the following position in the Video stream ( this mode of operation is not supported in the Square Pixel clock operation ).
EV A YC r SV A YC r
Y b/C /C r D ata#
525system
C b
Y
C b
Y
C r
Y
C b
Y
C r
Y
C b
Y
C b 0 0
Y 0 0
C r 0 0
Y 1 1
C b 1 1
360 720 360 721 361 722 361 723 360 720 360 721 361 722 361 723
368 736 368 366 732 366
855 428 856 428 857 861 431 862 431 863
D ata#
625system
C IN LK 33/ 25T(525/ 625) 276/ 288T(525/ 625) HI D 243/ 263T(525/ 625)
MS0413-E-03
24
2006 / 05
ASAHI KASEI ( 1 ) EAV Synchronization an EAV code which is encoded on input signal is decoded, and the device makes synchronization with its timing. EAV / SAV codes are as follows. Those codes succeeding 0xFF- 0x00- 0x00 which are fed as input data in 8-bit form become EAV / SAV codes. EAV / SAV codes have following meanings, starting with MSB. Bit Number WORD VALUE 0 0xFF 1 0x00 2 0x00 3 0xxx
here,
[AK8817]
MSB 7 1 0 0 1
6 1 0 0 F
5 1 0 0 V
4 1 0 0 H
3 1 0 0 P3
2 1 0 0 P2
1 1 0 0 P1
LSB 0 1 0 0 P0
F V
= 0 : Field 1 = 1 : Field 2 = 0 : other than Filed Blanking (V-Blanking) = 1 : Filed Blanking (V-Blanking)
H = 0 : SAV = 1 : EAV P3, P2, P1, P0 : Protection Bit Protection Bit and F / V / H relation is shown in the following table. F V H P3 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 At NTSC data input case Cb Y Cr Y 359 718 359 719 At PAL data input case Cb Y Cr Y 359 718 359 719 Cb 360 Y Cr 720 360 EAV Y Cr 720 360 EAV Y 721 Cb 428 P2 0 1 0 1 1 0 1 0 Y Cr 856 428 SAV Y Cr 862 431 SAV P1 0 0 1 1 1 1 0 0 Y 857 Cb 0 Y 0 P0 0 1 1 0 1 0 0 1 Cr 0 Y 1
......
Cb 360
Y 721
......
Cb 431
Y 863
Cb 0
Y 0
Cr 0
Y 1
MS0413-E-03
25
2006 / 05
ASAHI KASEI ( 1-1 ) EAV / SAV Code and Line Synchronization The AK8817 makes Vertical synchronization ( Line synchronization ) when F-bit in EAV makes transition from " 1 " to " 0 ". F-bit of EAV / SAV and Line relation is as follows F-bit NTSC PAL 0 Line4 - Line265 Line1 - Line312 Line266 - Line525 1 Line313 - Line625 Line1 - Line3 For reference, V-bit of EAV / SAV and Line relation is also shown below. Field V-bit NTSC PAL Start (V=1) Line1 - Line19 Line624 - Line625 - Line22 Field 1 End (V=0) Line20 - Line263 Line23 - Line310 Start (V=1) Line264 - Line282 Line311 - Line335 Field 2 End (V=0) Line283 - Line525 Line336 - Line623
1 2 3 4 5 6 7 8 9
[AK8817]
Digital Line-No.
F-bit 263 264 265 266
synchronization is made at this timing
Digital Line-No. F-bit
267
268
269
270
271
272
Line Synchronization by EAV at NTSC input case
Digital Line-No.
622
623
624
625
1
2
3
4
5
6
F-bit 310 311 312 313 314
synchronization is made at this timing
Digital Line-No. F-bit
315
316
317
318
319
Line Synchronization by EAV at PAL input
MS0413-E-03
26
2006 / 05
ASAHI KASEI
[AK8817]
(15) On-chip Color Bar The AK8817 can output Color Bar signal. Color Bar signal to be generated has 100 % amplitude and 75 % Saturation levels. Color Bar signal is output by setting register. When to output Color Bar signal, there are 2 modes of operation - one is external Sync timing mode for normal operation, and the other is internal self-operation mode. In internal self-operating mode, required timing is internally generated automatically. Namely, it is no need to input synchronization timing from outside of the chip. Operation mode setting is done by Control 1 Register . When BBG-bit is set, BBG-bit is prioritized ( Black Burst is output ).
WHITE 100%White
Synctip Level
YELLOW
CYAN
GREEN
MAGENTA
Cb Y Cr
WHITE 128 235 128
YELLOW 44 162 142
CYAN 156 131 44
GREEN 72 112 58
The following values are code for ITU-R. BT601 MAGENTA RED BLUE BLACK 184 100 212 128 84 65 35 16 198 212 114 128
(16) Black Burst Signal generation function The AK8817 can output Black Burst signal ( Black level output ). When to output Black Burst signal, there are 2 modes of operation - one is external Sync timing mode for normal operation , and the other is internal self-operation mode. In internal self-operation mode, required timing is internally generated automatically. Namely, it is no need to input synchronization timing from outside of the chip. When BBG-bit of [ Control 1 Register ] is set to "1", same operation is processed as in the case where fixed-16 Y signal and fixed-128 Cb / Cr signal outputs are input. Operation mode setting is done by Control 1 Register setting.
RED
BLUE
BLACK Blanking Level
MS0413-E-03
27
2006 / 05
ASAHI KASEI
[AK8817]
(17) Video ID The AK8817 supports to encode the Video ID ( EIAJ CPR-1204 ) which distinguishes the aspect ratio etc.. This is also used as CGMS ( Copy Generation Management System ). Turning "ON/OFF" of this function is made by setting both VMOD-bit = 0 and VBID-bit = 1 of { Control 1 Register (0x00) }. And data to be set is written into { VBID / WSS Data1 & 2 Registers ( 0x02,0x03 )}. Video ID information is the highest order of priority information among VBI information VBID Data Update timing .
VSYNC S et C ontro l R egister u-P D a ta N EW D AT A
DATA
O LD D A T A
N EW D AT A
VBID Code assignment 20 bit data is configured with WORD0 = 2 bit, WORD1 = 4 bit, WORD2 = 8 bit and CRC = 6 bit. CRC is automatically calculated and added by the AK8817. Default values of CRC polynomial expression X6 + X + 1 are all ones. -data configuration bit1 DATA WORD0 2bit VBID Waveform WORD1 4bit WORD2 8bit CRC 6bit bit20
Ref.
bit1 bit2 bit3
***
bit20
70IRE +/- 10IRE
0IRE + 10 IRE - 5 IRE
2.235usec +/- 50nsec 11.2usec +/- 0.3usec 49.1usec +/- 0.44usec 1H
Amplitude Encode Line
525/60 System 70IRE 20/283
MS0413-E-03
28
2006 / 05
ASAHI KASEI
[AK8817]
( 17 ) WSS function The AK8817 supports to encode the WSS ( ITU-R. BT.1119 ) which distinguishes the aspect ratio and sets CGMS-A etc.. Turning "ON/OFF" of this function is made by setting both VMOD-bit = 1 and WSS-bit = 1 of { Control 1 Register ( 0x00 ) }. And data to be set is written into { VBID / WSS Data1 & 2 Registers ( 0x02, 0x03 )}. WSS Data Update timing
VSYNC S et C ontro l R egister u-P D a ta N EW D AT A
DATA
O LD D A T A
N EW D AT A
WSS Waveform
500mV +/- 5% 0H
27.4usec 1.5usec 10.5usec 11.0 +/- 0.25usec 38.4usec 44.5usec
Encode line : former half of Line 23 ( Blank output during latter half ) Coding : Bi-phase modulation coding Clock : 5 MHz ( Ts = 200 nS ) Encoding details as follows Run-in 29 elements Start code 24 elements Group 1 Aspect ratio 24 elements Bit numbering 0123 LSB MSB 0 : 000111 1 : 111000 Group 2 Enhanced Services 24 elements Bit numbering 4567 LSB MSB 0 : 000111 1 : 111000 Group 3 Subtitles 18 elements Bit numbering 8 9 10 LSB MSB 0 : 000111 1 : 111000 Group4 Reserved 18 elements Bit numbering 11 12 13 LSB MSB 0 : 000111 1 : 111000
0x1F1C71C7
0x1E3C1F
MS0413-E-03
29
2006 / 05
ASAHI KASEI
[AK8817]
SYNC Signal waveform, Burst Waveform generator
(1) NTSC-J
S y n c r is e t im e
50% B u r s t H e ig h t
90% B u rs t H o r iz o n ta l r e f e r e n c e p o in t 50% 10% S yn c H . r e f . t o B u r s t S ta r t 50% S ync Le ve l
measurement point Total line period(derived) Sync Level Sync rise time Horizontal Sync width Horizontal reference point to burst start Burst * Burst Height ** 63.556 40 140 4.7 19 9 40
value
Consumer Quality tolerance +/- 3 Max 250 +/- 0.1 defined by SC/H +/- 1 +/- 3
units usec IRE nsec usec cycles cycles IRE
10% - 90% 50% 50% 50%
* there is a case where tolerance of Sync rise time is added to Sync width tolerance. * Measurement of Burst time length is made between the Burst start point which is defined as the zero-cross point, preceding the first half-cycle of the sub-carrier where Burst amplitude becomes higher than 50 % level and the Burst end point, defined in the same manner.
19 cycles +/-10
9 cycles +/- 1cycle
50%
NTSC Signal
MS0413-E-03
30
2006 / 05
ASAHI KASEI (2) Vertical Sync Signal timing ( NTSC )
3H 0 .5 H 3H 3H
[AK8817]
1
2
3
4
5
6
7
8
9
21
3H 0 .5 H
3H
3H
263
264
265
266
267
268
269
270
271
272
273
285
G
H
I
I
I
I
40IRE
+/-3IRE
Equalizing Pulse Equalizing Pulse and Serration Pulse
Symbol G H G I Pre-equalizing pulse width Vertical serration pulse width Post-equalizing pulse width Sync rise time Measurement point 50% 50% 50%
Serration Pulse
Value 2.3 4.7 2.3 140
Recommended tolerance +/- 0.1 +/- 0.2 +/- 0.1 Max 250
units usec usec usec nsec
* there is a case where tolerance of Sync rise time is added to Pulse width tolerance.
MS0413-E-03
31
2006 / 05
ASAHI KASEI (3) PAL-B,D,G,H,I
[AK8817]
S y n c r is e t im e
50% B u r s t H e ig h t
90% B u rs t H o r iz o n ta l r e f e r e n c e p o in t 50% 10% H o r iz o n ta l S y n c H . r e f . t o B u r s t S ta r t 50% S yn c L e ve l
measurement point Total line period(derived) Sync Level Sync rise time Horizontal Sync width Horizontal reference point to burst start Burst * Burst Height **
value 64.0 300 0.2 4.7 5.6 10 300
Consumer Quality tolerance +/- 20 Max 0.3 +/- 0.2 +/- 0.1 +/- 1 +/- 30
units usec mV usec usec usec cycles mV
10% - 90% 50% 50% 50%
* there is case where tolerance of Sync rise time is added to Sync width tolerance.
MS0413-E-03
32
2006 / 05
ASAHI KASEI (4) Vertical Sync Signal timing and Burst Phase PAL-B,D,G,H,I
A B
[AK8817]
308
309
310
311
312
313
314
315
316
317
318
319 A
320 B
321
322
620
621
622
623
624
625
1
2
3
4
5
6 A
7 B
8
308
309
310
311
312
313
314
315
316
317
318 A
319 B
320
321
322
620
621
622
623
624
625
1
2
3
4
5
6
7
8
A : Phase of Burst : nominal Value + 135 B : Phase of Burst : nominal Value - 135 Since Burst frequency and Line frequency are not practically in integer-multiple relation, specified phase value is not exactly 135 degrees. Diagram below shows phase direction.
G
H
I
I
I
I
300mV
+/-30mV
Equalizing Pulse Equalizing Pulse and Serration Pulse
Serration Pulse
Symbol G H G I Pre-equalizing pulse width Vertical serration pulse width Post-equalizing pulse width Sync rise time
Measurement point 50% 50% 50%
Value 2.35 4.7 2.35 200
Recommended tolerance +/- 0.1 +/- 0.2 +/- 0.1 Max 300
units usec usec usec nsec
* there is a case where tolerance of Sync rise time is added to Pulse width tolerance.
MS0413-E-03
33
2006 / 05
ASAHI KASEI
[AK8817]
Register Map
Address 0x00 0x01 0x02 0x03 0x04 0x05 Register Control 1 Register Control 2 Register VBID/WSS Data 1 Register VBID/WSS Data 2 Register Input Control Register Device ID & Revision ID Register Default 0x00 0x00 0x00 0x00 0x00 0x17 R/W R/W R/W R/W R/W R/W R Function Mode set Register Mode set Register VBID data is set, WSS data is set VBID data is set, WSS data is set Input control register for out-of-standard quality input signal Register for Device ID and Revision ID
MS0413-E-03
34
2006 / 05
ASAHI KASEI Control 1 Register (R/W) [Address 0x00] Sub Address 0x00 bit 7 bit 6 DAC BBG 0 0
[AK8817]
bit 5 CBG 0
bit 4 bit 3 MASMD WSS Default Value 0 0
bit 2 VBID 0
bit 1 SCR 0
Default Value 0x00 bit 0 VMOD 0
Control 1 Register Definition BIT Register Name bit 0 bit 1 bit 2 bit 3 VMOD SCR VBID WSS Video Mode bit Sub-Carrier Reset bit VBID Set bit WSS Set bit
R/W R/W R/W R/W R/W
bit 4
MASMD
Master Mode bit
R/W
bit 5 bit 6 bit 7
CBG BBG DAC
Color Bar Generator bit Black Burst Generator bit DAC Set bit
R/W R/W R/W
Definition 0: NTSC 1: PAL 0 : Sub-Carrier Reset 1 : Sub-Carrier Reset off 0 : VBID OFF 1 : VBID ON 0 : WSS OFF 1 : WSS ON Master Mode bit to set Sync mode when Color Bar signal and Black Burst signal are generated 0 : operation by an external Sync timing 1 : operation by an internal self-operating mode ( master mode ) note ) Master mode bit is still valid in normal data input, but output video is not synchronized. 0: OFF 1: ON when BBG is set, BBG is prioritized. 0 : OFF 1 : ON 0 : DAC OFF 1 : DAC ON
MS0413-E-03
35
2006 / 05
ASAHI KASEI Control 2 Register (R/W) [Address 0x01] Sub Address 0x01 bit 7 bit 6 Reserved Reserved 0 0
[AK8817]
bit 5 Reserved 0
bit 4 bit 3 VAMPMD1 VAMPMD0 Default Value 0 0
bit 2 SETUP 0
Default Value 0x00 bit 1 bit 0 REC656 PIXRT 0 0
Control 2 Register Definition BIT Register Name bit 0 PIXRT Pixel Rate Set bit
R/W R/W
bit 1
REC656
Rec656 Set bit
R/W
bit 2
SETUP
Setup bit
R/W
bit 3 ~ bit 4 bit 5 ~ bit 7
VAMPMD0 ~ VAMPMD1
VIdeo Amp Mode Set bit
R/W
Definition Pixel rate setting is done. 0 : ITU-R BT.601 data input ( at 27 MHz rate ) 1 : Square Pixel data input NTSC : 24.5454 MHz PAL : 29.50 MHz Synchronization mode setting is done. 0 : synchronization is made with HDI / VDI input. 1 : synchronization is made with ITU-R BT.656 data input Set-up setting is done 0 : with no set-up 1 : with 7.5 IRE set-up Operation mode for Video Amp. VAMPMD[1:0] 00: Video Amp OFF + SAG Compensation OFF 01: Video AMP ON + SAG Compensation ON 10: Video Amp ON + No SAG Compensation 11: Reserved Set "0"
Reserved
Reserved bit
R/W
MS0413-E-03
36
2006 / 05
ASAHI KASEI VBID/WSS 1 Register (R/W) [Address 0x02] VBID/WSS 2 Register (R/W) [Address 0x03]
[AK8817]
Video ID and WSS data setting are made. A common data register is used for both video ID and WSS data. When VBID bit of mode register is set in NTSC mode, data is for VBID data ,and when WSS bit of Control 1 Register is set in PAL mode, data is for WSS data. When VBID-bit is "1" and VMOD-bit is "0" in Control 1 Register , the following bits are assigned. Sub Address 0x02 bit 7 bit 6 VBID7 VBID8 0 0 default Value 0x00 bit 1 bit 0 VBID13 VBID14 0 0 default Value 0x00 bit 0 VBID6 0
bit 5 VBID9 0
bit 4 bit 3 VBID10 VBID11 Default Value 0 0
bit 2 VBID12 0
Sub Address 0x03 bit 7 bit 6 Reserved Reserved 0 0
bit 5 VBID1 0
bit 4 bit 3 VBID2 VBID3 Default Value 0 0
bit 2 VBID4 0
bit 1 VBID5 0
Note ) "0" should be written into reserved bits. VBID1 ---- VBID14 above correspond to the bit 1 ---- bit 14 which are described at { VBID Data Code Assignment } in { ( 14 ) Video ID } section. A 6-bit CRC code from bit 15 ~ bit 20 is automatically added by the AK8817. Data is retained till data is updated to a new one. Following bits are assigned when WSS-bit is "1" and VMOD-bit is "1" in Control 1 Register . Sub Address 0x02 bit 7 bit 6 G2-7 G2-6 0 0 default Value 0x00 bit 0 G1-0 0 default Value 0x00 bit 0 G3-8 0
bit 5 G2-5 0
bit 4 bit 3 G2-4 G1-3 Default Value 0 0
bit 2 G1-2 0
bit 1 G1-1 0
Sub Address 0x03 bit 7 bit 6 Reserved Reserved 0 0
bit 5 G4-13 0
bit 4 bit 3 G412 G4-11 Default Value 0 0
bit 2 G3-10 0
bit 1 G3-9 0
Note ) WSS data is written with 0x01 first, then 0x02 in this order. When the 2nd byte ( 0x02 ) of WSS data is written, the AK8817 interprets that data is updated to a new one and then encodes it to the next video line ( Line 23 ). Data is retained till data is updated to a new one.
MS0413-E-03
37
2006 / 05
ASAHI KASEI Input Control Register (R/W) [Address 0x04] This is an out-of-standard quality input signal control register. Sub Address 0x04 bit 7 bit 6 Reserved CBCR 0 0
[AK8817]
bit 5 VD2 0
bit 4 VD1 0
bit 3 VD0 0
bit 2 HD2 0
default Value 0x00 bit 1 bit 0 HD1 HD0 0 0
Adjustment of Sync input timing is made. BIT Register Name HD0 bit 0 ~ HDI Input Delay ~ HD2 bit 2 VD0 bit 3 ~ VDI Input Delay ~ VD2 bit 5 bit 6 CBCR Exchange CbCr bit 7 Reserved Reserved
R/W R/W
Definition HDI signal input is delayed by the set value. HD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay ) VDI signal input is delayed by the set value. VD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay ) Cb, Cr timing data are interchanged at CBCR = 1. Reserved
R/W R/W R/W
MS0413-E-03
38
2006 / 05
ASAHI KASEI Device ID and Revision ID Register (R) [Address 0x05] Register to show Device ID & Revision of the AK8817. Device ID for AK8817 is 0x17(decimal) Initial Version of the Revision ID is 0x00. Revision number is modified only when a control software needs to be modified. Sub Address 0x5 bit 7 bit 6 Rev1 REV0 0 0
[AK8817]
bit 5 DEV5 0
bit 4 DEV4 1
bit 3 DEV3 0
bit 2 DEV2 1
bit 1 DEV1 1
default Value 0x17 bit 0 DEV0 1
Device ID and Revision ID Register Definition BIT Register Name DEV0 bit 0 ~ Device ID bit ~ DEV2 bit 5 bit 6 ~ bit 7 REV0 ~ REV2 Revision ID bit
R/W R
Definition To show Device ID Device ID is 0x17h. To show Revision information Revision ID is updated when software modification is to be expected. It is 0x00.
R
MS0413-E-03
39
2006 / 05
ASAHI KASEI
[AK8817]
System Connection Example
AK8817 PVDD HSYNC VSYNC D[7:0] PVDD Clock PVSS HDI VDI CLKIN DACOUT u-P I2C SDA SCL RSTN PDN Digital 3.0V DVDD DVSS TEST ATPG CLKINV
AVSS AVDD
SAG
1uF
VOUT 47uF 75 ohm
390ohm VREF 0.1uF
IREF
12kohm
Analog 3.0V
0.1uF DVSS AVSS
10uF
MS0413-E-03
40
2006 / 05
ASAHI KASEI
[AK8817]
Package Drawing
41pin FBGA
4.0 0.1 41 - 0.3 0.05 0.05
M S AB 7 6 5 4 3 2 1 A B
A
B
4.0 0.1
C
3.0
D E F G
0.5 3.0
0.5
S
0.25 0.05
1.0MAX
0.08 S
Package & Lead frame material
Package molding compound: Interposer material: Solder ball material: Epoxy BT resin SnAgCu
MS0413-E-03
41
2006 / 05
ASAHI KASEI
[AK8817]
Package Marking Drawing
8817 XXXX
a. Package Type: b. Number of Pins: c. Product Number: d. Control Code:
BGA 41pins (Including INDEX pin ) 8817 XXXXX (4 digits)
MS0413-E-03
42
2006 / 05
ASAHI KASEI MS0413-E-01 2006/1 Block Diagram is revised. MS0413-E-02 P.4 Before F1 After F1 P.8 AC Timing CLK Before CLKINV I Internal clock is inverted (internal operation timing edge is inverted.) Connect to either PVDD or PVSS(DGND). 2006/4
[AK8817]
CLKINV
I
Internal clock is inverted (internal operation timing edge is inverted.) Connect to either DVDD or DGND.
fCLKI tCLKIL tCLKIH
1/2 DVDD VIH
CLKIN
VIL
After
fCLKI tCLKIL tCLKIH
1/2 PVDD VIH
CLKIN
VIL
MS0413-E-03
2006/5
Appending Before Note1) operation at 27 MHz, NTSC mode on-chip 75% color bar output is enabled and Video Amp output is " on " ( no external output loads are connected , other than those recommended, connecting-components ). After Note1) operation at 27 MHz, NTSC mode on-chip 75% color bar output is enabled and Video Amp output is " on " ( no external output loads are connected except for recommended components. ). 15pF capacitors in following figure represent PCB layout-capacitor.
MS0413-E-03
43
2006 / 05
ASAHI KASEI
[AK8817]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0413-E-03
44
2006 / 05

▲Up To Search▲

Price & Availability of AK8817VG

	To Download AK8817VG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .